A pipeline ADC (analog to digital converter) is generally preferred to achieve a speed of 100 MSPS (mega samples per second) in high speed applications. However in recent years, with the advent of UDSM (ultra deep sub micron) technologies and improved capacitor matching techniques, Successive approximation register analog to digital converter (SAR ADC) is a fast emerging alternative to the pipeline ADCs. The fact that pipelined ADCs require active amplifiers which comes at the cost of high power makes SAR ADCs a good architectural choice as its static power requirement is limited to a comparator which consumes a low power. The other type of power consumption in SAR ADCs is switching power consumption or dynamic power consumption. The switching power consumption is directly proportional to voltage, frequency and capacitance of the SAR ADC. If the frequency of the SAR ADC is reduced, it proportionately reduces the switching power consumption in the SAR ADC. A digital value stored in an n-bit successive approximation register (SAR) is input to a digital-to-analog converter, and a decision is made as to whether the value in the SAR represents an analog voltage that is higher or lower than an input analog value.
In an N-bit SAR ADC, the analog to digital conversion is done serially and hence requires N steps. Thus, a SAR ADC seeking to produce a 10 bit output has to perform 10 bit trials. Therefore, the SAR ADCs are inherently slow. In high speed applications, for example application at 100 MSPS throughput with 10 bit resolution, the SAR ADC is required to operate at 1 GHz. The SAR ADCs require one to two error correction cycles which further pushes the speed of operation and hence increase the dynamic power consumption in the SAR ADC. To resolve this issue, a coarse ADC or a flash ADC is used to resolve first few bits corresponding to the input analog value and then a SAR ADC is used to further resolve an output of the coarse ADC to a fine level. The resolution of first few bits by a coarse ADC relaxes the high speed requirements of a SAR ADC thereby reducing the dynamic power consumption. The coarse ADC is a fast ADC as it includes a plurality of comparators which are used to quickly resolve few bits of the N bit SAR ADC. However, a coarse ADC cannot be used for higher resolution as it would directly increase the number of comparators which will impact the area and power margins severely. Therefore, a combination of coarse ADC and SAR ADC is used for effective analog to digital conversion. For example, in a 10 bit SAR ADC, a coarse ADC is used to resolve first 2 bits (4 comparators) or first 3 bits (8 comparators). However, there are inherent problems in combining the coarse ADC and the SAR ADC.